General Summary:
Worked on coverage driven module verification.
Strong in System Verilog, UVM
Sound experience in testbench (stimulus, agent, monitor, checker) development.
Failure debugging with Verdi & log file.
Worked in the verification having c based reference model inside the testbench
Experience with assertion development.
Familiar with the EDA tools IUS, VCS, Verdi etc.
Exposure in scripting(perl, Python).
Good team player. Need to interact with the designers and other verification engineers proactively.
Prior experience with video pipeline is added advantage.
Knowledge of tensilica
Worked with sub-system verification with tensilica
Experience in C based system modelling.
Debug with C based reference model.
Minimum Qualifications:
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