Job Details:Job Description: Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
Qualifications:B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 8+ years of DFT experienceJob Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:India, HyderabadBusiness group:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
