Digital Bench Characterization Engineer – DDR and High-Speed IO interface (1-3 years)

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Title

Digital Bench Characterization Engineer – DDR and High-Speed IO interface (1-3 years)

Location
India - Bangalore
Job Overview

The BDC Post Silicon Engineering group has an opening for a Digital Bench characterization Engineer. This group develops Test solutions for Design verification of Highly integrated SOC’s (System on Chip) designed by Qualcomm. We work with Design, System, Program Management, Yield, Reliability and Manufacturing teams to Test, support and commercialize Qualcomm’s products.

As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, clocking architecture, Delay circuits, Power Distribution Network) and High-Speed IO interfaces (PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of DDR & High-Speed IO IP’s and perform failure analysis to root-cause a design problem. You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment.

Education Requirements

MTech, BTech or Equivalent in Electronics or Electrical Engineering with 1-3 years of related work experience
Skills/Experience:

• Solid understanding of Electronics engineering fundamentals, DDR & High-Speed IO circuit analysis techniques and Semiconductor manufacturing process,
• Good understanding of Test and characterization methodology of DDR and High-Speed IO interfaces 
• In-depth understanding of Mobile & PC DDR 2/3/4 protocol, timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding).
• Hands-on experience using Bench instruments such as oscilloscopes, J-BERT, network / spectrum analyzers, signal generators and Logic analyzers is a must.
• Solid software skills for writing and debugging Test code using C, C# or Python. LabView knowledge is a plus.
• Using CAD software such as Mentor Graphics DA or Cadence Allegro is a plus.
• Ability to work effectively in a fast-paced environment with strong verbal and written communication skills.

Keywords
DDR, High-Speed IO, Electrical Spec compliance, Eye Diagram, Jitter, C, C#, Python, LabVIEW

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email toaccommodationsupport

Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found herefor assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.

Qualcomm is an equal opportunity employer and supports workforce diversity.

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