Director, IP Design/Implementation Engineering

Role Summary:

We are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design. 

MME's Digital IP team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.

Job Responsibility:

• Drive architecture definition in conjunction with the Systems Architects, and working with the cross function teams both on Design, Verification, Validation and supporting SW/FW teams.
• Drive compliance testing and assuring quality, meeting KPI’s and target performance.
• Play key team member role in SOC & digital IPs development from Micro-Architecture to RTL implementation
• Hands on involvement in IP & SOC digital design/Integration
• Translate Micro-Architecture specification to Implementation specification.
• Actively drive in technical challenges discussion and decision making within IP scope.
• Delivery of SOC with first time right quality meeting project schedule
• Grow the team appropriately to meet the roadmap requirements within cost constraints
• Raise the bar in terms of project execution
• Build and develop the team to ensure the next level of technical leaders and managers

Job Qualification:

• BSEE required, MSEE preferred with 15+ years of industry related experience
• Ability to lead and motivate technical teams to develop industry-leading IP using cutting-edge methodologies
• Must have experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies
• Earlier experience with SoC Processor based architectures needed. ARM experience would be added advantage
• Self-driven and capable for independent work and independent decision making.
• Knowledge in frontend design experience on IPs involve ARM processor based sub-system, Serial Standard interfaces, Memory controllers
• Exposure to Low-power design, System Security considered as added advantage
• Hands on front-end design of complex multi clock domain blocks
• Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
• Experience in Spyglass for lint and CDC checks.
• Experience in using Cadence RC for synthesis and LEC flow.
• Experience in identifying and implementing complex ECO in netlist.
• Knowledge on Verification Methodologies to actively participate in Debug Analysis
• Develop new IP and enhance existing IP and sub-systems.
• Develop both foundation IP and differentiating/market-oriented IP and maintain forward looking roadmaps
• Excellent written and verbal communication skill.

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