IBM LOGIC DESIGN ENGINEER – Processor Coherency Logic

Your role and responsibilities

*Lead the design and development of on- and off-chip network microarchitectures for Coherency and data transport that meet KPIs for next-generation SMP.
* Work closely with Cache/Nest PD architect & designers to implement structures/topologies that are logically and physically realizable by the target tape-out date.
* Modify/develop Cache Coherence protocol that best supports coherence transport topology.
* Develop features in L2 and LLC micro architectures that improve KPIs.
* Work with Core Architects & Designers to implement features in L2-Core interface and interactions, that improves KPIs.

Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise

* Minimum 8 to 12 years of relevant experience
* Hands-on RTL level experience of independently delivering Coherency feature in processor
* Expertise in Cache Coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP
* Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations
* Experience in working with Core architecture/ FW/ SW teams
* Exposure to System microarchitecture

Preferred technical and professional experience

- Knowledge of Memory Management units, Data transfer protocols

- Knowledge of CDC, RDC concepts

- Knowledge of verification principles and coverage

- High-level knowledge of Linux operating system

- Knowledge of one object oriented language and scripting language
-Understanding of Agile development processes
- Experience with DevOps design methodologies and tools