Job Details:

Job Description: Candidate should be perusing a Master's Degree in Electronics/VLSI/Computer Engineering. Strong Digital Design concepts are desired and an ability to learn how to translate them into RTL using System Verilog should be demonstrated. Interest in automation using PERL/Python will be an added advantage. Candidate should possess a Master Degree in Electrical/Computer Engineering with 1-2 years' experience on working in Soft IP Development area and contributing towards logic design by developing micro architectural specification from high level architectural specification, coding the RTL, running the various design tools to qualify the IP to delivery standards, creating timing collateral, waivers and supporting various SoC with the usage and deployment of the Soft IP. Experience on functional bus protocols, IEEE standards for test such as JTAG etc. is highly beneficial. Internship experience in a leading VLSI company is preferred.

Qualifications:

Minimum Qualifications
- Technical proficiency and a strong understanding of engineering principles, methodologies, and tools.
- Demonstrated ability to solve technical problems and apply innovative solutions.
- Proficiency in relevant software, tools, or coding languages as required by the role.
- Certification in related technical fields as appropriate for the position.
Preferred Qualifications
- Strong analytical, organizational, and project management skills.
- Effective collaboration and communication abilities to work within team environments.
- A passion for innovation, creativity, and staying ahead of industry trends.
- Experience contributing to projects with measurable outcomes and success metrics.
Candidate should possess a Bachelor's degree or Master's in Electrical Engineering Degree in Electrical/Computer Engineering with 1-2 years' experience on working in Soft IP Development area and contributing towards logic design by developing micro architectural specification from high level architectural specification, coding the RTL, verifying it, creating testbenches, running the various design tools to qualify the IP to delivery standards, creating timing collateral, waivers and supporting various SoC with the usage and deployment of the Soft IP. Experience on functional bus protocols, IEEE standards for test such as JTAG etc. is highly beneficial. Internship experience in a leading VLSI company is preferred.
If you are ready to make a meaningful impact, collaborate with talented professionals, and grow your career in a supportive and innovative environment, we encourage you to apply today.

Job Type:Intel Contract Employee

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:



Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.