Job Details:

Job Description:

We are seeking a Senior RTL Design Engineer with 2+ years of experience to drive the logic design and integration of our next-generation, high-speed Mixed-Signal IP. In this role, you will bridge the gap between digital architecture and analog mixed-signal (AMS) circuits, taking ownership of critical digital blocks that control, calibrate, and interface with high-speed SerDes components.
You will collaborate closely with analog designers, verification engineers, and architectural teams to deliver robust, power-efficient, and highly optimized silicon IPs compliant with the latest specifications.
Key Responsibilities
RTL Development: Own the micro-architecture and RTL design (using System Verilog/Verilog) for digital control blocks within the PHY, including PCS (Physical Coding Sublayer), calibration engines, power management states (L0s, L1, L2), and clock/reset distribution.
Mixed-Signal Interface and Integration: Define, design, and verify the digital-analog interface boundary. Implement complex calibration algorithms for analog components (e.g., RX equalization, TX driver impedance, PLL/DLL tracking loops).
IP Compliance: Ensure the digital logic seamlessly integrates with the Data Link layer via standard interfaces (such as PIPE 5.x/6.x) and strictly adheres to protocol constraints.
Front-End Implementation: Drive design closure activities including Linting, Clock Domain Crossing (CDC) analysis, Formal Verification (LEC), and Static Timing Analysis (STA) constraints generation.
Collaboration and Debug: Work hand-in-hand with Analog Mixed-Signal (AMS) simulation teams and Design Verification (DV) teams to debug complex co-simulation failures and maximize functional coverage.
Silicon Power-On Support: Support post-silicon validation, bring-up, and debug teams to root-cause silicon misbehavior and optimize firmware/hardware calibration parameters.

Qualifications:Experience: Minimum 2+ years of dedicated experience in ASIC/IP RTL design. Protocol and Domain Expertise: Strong working knowledge of high-speed SerDes architectures. Deep understanding of the PIPE interface standard. Mixed-Signal Familiarity: Proven experience dealing with digital/analog boundaries, including handling asynchronous signals, handshaking protocols, and managing distinct analog/digital power domains. Design Automation: Proficiency with industry-standard front-end design tools (e.g., Synopsys SpyGlass for Lint/CDC, Cadence JasperGold for formal verification, or similar). Low Power and Timing: Solid understanding of multi-clock designs, low-power design techniques (UPF, clock gating), and synthesis/STA fundamentals. Education: Bachelor's or Master's degree in Electrical Engineering, Electronics and Communication, or a related discipline.



Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:



Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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