This role is for one of the Weekday's clients Salary range: Rs 1500000 - Rs 3000000 (ie INR 15- 30 LPA) Min Experience: 8+ years Location: Bengaluru JobType: full-time We are looking for an experienced Verification & Validation Engineer with deep expertise in GPU architectures and AI accelerators to join our hardware engineering team.
In this role, you will be responsible for verifying next-generation compute architectures that power high-performance graphics, machine learning, and AI workloads.
You will work closely with architects, RTL designers, firmware teams, and software engineers to ensure the functional correctness, performance, and reliability of advanced GPU and AI accelerator designs.
The ideal candidate has a strong background in SoC or IP verification, hands-on experience with industry-standard verification methodologies, and a proven track record of delivering high-quality silicon for complex compute platforms.
Key Responsibilities Develop and execute comprehensive verification strategies for GPU, AI accelerator, and compute IP blocks.
Design, implement, and maintain SystemVerilog/UVM-based verification environments, reusable testbenches, and verification components.
Create directed and constrained-random test cases to validate functionality across various design scenarios.
Develop verification plans, test plans, coverage models, and closure strategies to ensure complete functional verification.
Perform functional, code, assertion, and toggle coverage analysis to achieve verification signoff.
Debug RTL, simulation failures, protocol violations, and complex design issues using waveform analysis and debug tools.
Collaborate with architecture, RTL design, firmware, compiler, and software teams to understand specifications and resolve design issues.
Validate AI accelerator features including matrix computation engines, tensor processing units, memory hierarchies, scheduling logic, and data movement.
Verify GPU subsystems including shader pipelines, cache hierarchy, memory interfaces, DMA engines, and interconnect protocols.
Develop assertions and formal verification checks to improve design quality.
Support regression automation, continuous integration, and verification infrastructure improvements.
Participate in design reviews, architecture discussions, and silicon bring-up activities.
Mentor junior verification engineers and contribute to verification methodology enhancements.
Required Skills & Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
8–12 years of experience in ASIC, SoC, or IP Verification.
Strong expertise in GPU architecture verification .
Hands-on experience verifying AI accelerators , machine learning hardware, or tensor processing architectures.
Strong proficiency in SystemVerilog and UVM .
Solid understanding of constrained-random verification methodologies.
Experience writing assertions using SystemVerilog Assertions (SVA) .
Strong debugging skills with simulation and waveform analysis tools.
Experience with functional coverage, coverage closure, and regression management.
Familiarity with scripting languages such as Python, Perl, or Shell for automation.
Understanding of memory subsystems, cache coherency, NoC, DMA, and high-speed interfaces.
Knowledge of industry-standard protocols such as AXI, AHB, APB, PCIe, or similar.
Experience using EDA verification tools from Synopsys, Cadence, or Siemens EDA.
Preferred Qualifications Experience verifying high-performance computing (HPC) or heterogeneous compute architectures.
Familiarity with formal verification methodologies.
Understanding of AI/ML workloads, deep learning frameworks, and accelerator architectures.
Exposure to silicon validation, post-silicon debugging, or emulation platforms.
Experience working with multi-core SoCs and complex compute subsystems.
Knowledge of performance verification and power-aware verification techniques.
