Job description
This role is for one of the Weekday's clients Salary range: Rs 200000 - Rs 4000000 (ie INR 2-40 LPA) Experience: 3+ yrs Location: Hyderabad Job Type: full-time We are seeking a highly skilled Analog Layout Engineer with strong expertise in AMS Layout , Virtuoso , and PLL circuit layout design to join a high-performance semiconductor engineering team.
This role involves developing complex custom analog and mixed-signal layouts for advanced technology nodes while ensuring optimal performance, manufacturability, and reliability.
As an Analog Layout Engineer, you will work closely with circuit designers, verification engineers, and physical design teams to translate schematic requirements into high-quality silicon-proven layouts.
You will play a critical role in delivering analog and mixed-signal IPs by implementing precision layout techniques, optimizing area and matching characteristics, and ensuring compliance with foundry design rules.
The ideal candidate possesses a strong understanding of analog layout fundamentals, device matching, parasitic effects, and layout optimization techniques.
Experience with critical analog building blocks such as PLLs , ADCs , DACs , and LDOs will be highly valued.
This role offers the opportunity to work on cutting-edge semiconductor products and contribute to the development of next-generation integrated circuits used in high-performance applications.
Key Responsibilities Design and develop high-quality custom analog and mixed-signal layouts using Cadence Virtuoso .
Create and optimize layouts for critical analog circuits including PLLs, ADCs, DACs, LDOs , voltage references, bias circuits, and other AMS blocks.
Interpret circuit schematics and collaborate with design engineers to understand performance requirements and layout constraints.
Apply advanced layout techniques such as common centroid structures, interdigitated layouts, shielding, guard rings, matching strategies, and noise isolation methods.
Perform layout planning, floorplanning, and area optimization while meeting performance, power, and reliability requirements.
Execute layout verification tasks including DRC, LVS, ERC, and parasitic extraction checks.
Analyze post-layout parasitic effects and work closely with circuit designers to achieve design closure.
Ensure layouts comply with foundry design rules, reliability requirements, and manufacturing guidelines.
Support tape-out activities and coordinate with verification and physical design teams throughout the design cycle.
Participate in design reviews and provide recommendations to improve layout quality and silicon performance.
Debug layout-related issues and implement corrective actions to meet project schedules and quality targets.
Document layout methodologies, best practices, and design guidelines to support engineering excellence and knowledge sharing.
What Makes You a Great Fit Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, Electrical Engineering, or a related field.
3+ years of hands-on experience in analog and mixed-signal layout design.
Strong expertise in Cadence Virtuoso and custom layout development.
Proven experience designing layouts for PLL (Phase Locked Loop) circuits and other high-performance analog blocks.
Deep understanding of analog layout concepts including device matching, symmetry, routing techniques, electromigration, latch-up prevention, and substrate noise mitigation.
Experience with layout verification flows including DRC, LVS, ERC, and parasitic extraction.
Knowledge of advanced semiconductor process technologies and foundry requirements.
Familiarity with ADC, DAC, and LDO layouts is highly desirable.
Strong problem-solving skills with the ability to optimize layouts for performance, area, and manufacturability.
Experience working closely with analog circuit designers through the complete design cycle from concept to tape-out.
Ability to manage multiple design assignments while maintaining high quality and meeting project deadlines.
Strong communication and collaboration skills in cross-functional engineering environments.
This job post has been translated by AI and may contain minor differences or errors.
