Debug and interconnect Design Lead

Debug and interconnect Design Lead/Methodology

Business Line Description:
NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Edge, and Radar Processing business lines. MME's SoC Hardware Architecture team produces architectural solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.

Jobs Summary

SoC Debug is very crucial in chip design as it helps identify and resolve issues that

can arise during the development and post silicon testing. Effective and consistent SoC Debug infrastructure ensures the functionality, performance, and reliability of the chip. It helps in pinpointing and fixing errors, optimizing power consumption, and enhancing overall system integration. SoC debug plays a vital role in delivering high-quality, reliable, SoCs to our customers in reducing the time to market.

This position will be

·Deep understanding of SoC debug aspects ARM debug infrastructure (including CoreSight infrastructure, SoC Cross Trigger Matrix, JTAG-based debug implementation and/or validation)

·Understand interconnect protocols like AHB/AXI/ACE/ACE-Lite/NoC concepts.

·Familiarity with 3rd Party tools like Arteris FlexNoC, ARM Socrates etc

·Develop executable architecture specifications, automate the flow from definition to design delivery.

·Proficiency in scripting languages like PERL/Python is required

·Able to define and create a methodology, automation frame work for debug in all SoCs

·Collaborate with other SoC Architecture teams/Software/FE teams and drive co-design and collaboration on features set. 

·Post-Silicon production support with silicon debug

·Industry standards tracking & 3rd party IP technical evaluation. 

·Well versed with Knowledge of SoC clocking and reset mechanisms would also be advantageous

Key Challenges:

·Experience in designing or architecting complex SoCs in leading-edge process nodes with multiple independent compute environments

·Exposure to ISO26262-compliant and mixed-criticality architectures

·Ability to work at the system level, identifying optimal partitioning of solutions between hardware and software, working closely with software architects

·Track record of assessing performance, power, and area tradeoffs and determining the correct balance for a given product type

·Experience in defining IP components to solve system issues.

·High motivation and results orientation

·Strong problem-solving skills

·Excellent interpersonal skills, including written and verbal communication

·Teamwork, negotiation, and presentation skills

·Willing and able to mentor junior engineers

Job Qualifications:

·BTech/MTech/Ph.D. in Electrical/Computer Engineering or other similar disciplines with at least 8 years of relevant experience.  

·Understand interconnect protocols like AHB/AXI/ACE/ACE-Lite/NoC concepts.

·Good knowledge of Digital Design and RTL development - Hands-on experience with SoC Design, Verilog RTL coding

·Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols, and virtualization

·Working knowledge of Synthesis, DFT, verification, and silicon debug.

·Working knowledge of Lint, CDC, PLDRC, CLP, etc

·Basic Knowledge of System Architecture

·Familiarly with system design, SOC micro-architecture, and/or design

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