Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your role and responsibilities
We are seeking a hands-on engineer with strong expertise in Structural Design-for-Test (DFT) to drive scan, ATPG, and test protocol validation across pre-silicon and post-silicon phases. The ideal candidate will play a key role in enabling high test coverage, debugging structural test failures, and ensuring robust DFT infrastructure across complex SoCs.
This role focuses onensuring high-quality structural test coverage and robust DFT infrastructure for complex SoCs. You will work across design, verification, validation, and product engineering teams to enable efficient test, debug, and yield improvement, playing a critical role in delivering production-quality silicon.
Key Responsibilities

• Develop and validate structural test strategies including scan, ATPG, and boundary scan
• Drive scan chain bring-up, debug, and validation on silicon and emulation platforms
• Generate, debug, and optimize ATPG patterns for stuck-at, transition, and path delay faults
• Perform coverage analysis and implement improvements through test point insertion and design enhancements
• Debug scan failures, chain integrity issues, and pattern mismatches (shift/capture failures)
• Develop and validate JTAG (IEEE 1149.1) and IEEE 1500 test access mechanisms
• Work on boundary scan validation and board-level test enablement
• Configure and validate eFuse programming flows and test-related fuse controls
• Support RRFA (Root Cause Failure Analysis) and structural failure diagnosis on silicon
• Collaborate with physical design teams for scan stitching, congestion, and timing closure impacts
• Analyze logs, waveforms, tester data (ATE), and debug infrastructure outputs
• Ensure proper implementation of test modes, clocking, resets, and power domains for DFT

Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise

• Strong understanding of structural DFT concepts:
  • Scan design and architecture
  • ATPG (stuck-at, transition, path delay)
  • Fault modeling and coverage metrics
• Hands-on experience with:
  • Scan chain debugging and validation
  • ATPG pattern generation and failure diagnosis
  • Test point insertion and coverage improvement techniques
• Expertise in industry-standard protocols:
  • JTAG (IEEE 1149.1)
  • IEEE 1500 (core test wrappers)
  • Boundary Scan (1149.x family)
• Experience in coverage analysis, diagnosis, and yield correlation
• Knowledge of eFuse architectures and programming/debug flows
• Familiarity with RRFA / failure debug methodologies
• Ability to read and debug Verilog RTL/netlists for DFT logic
• Understanding of chip internals (clock/reset, power domains, test modes)

Preferred technical and professional experience

• Experience with leading DFT toolchains:
  • Tessent, Modus, DFTMAX, or equivalent
• Exposure to:
  • Scan compression architectures
  • Diagnosis and volume scan analytics
  • Power-aware ATPG and IR-drop mitigation techniques
• Experience in:
  • Post-silicon validation and ATE bring-up/debug
  • Pre-silicon DFT verification and emulation
• Familiarity with:
  • Debug infrastructure and trace collection tools
  • Firmware interaction with test modes and fuse programming
• Proficiency with scripting (Python, Tcl) and version control (Git)

Nice-to-Have (Value Add)

• Experience with advanced fault models (cell-aware, bridging faults)
• Knowledge of hierarchical DFT and SoC integration challenges
• Exposure to automotive/safety standards (e.g., ISO 26262)
• Experience in yield ramp, silicon learning, and RMA debug flows

Years of Experience:
3-5