Job description
This role is for one of the Weekday's clients Experience: 3+ yrs Location: Bengaluru Job Type: full-time We are seeking a highly motivated and experienced DFT (Design for Testability) Engineer to join our semiconductor design team.
The ideal candidate will have strong expertise in DFT architecture, scan implementation, and test methodologies for complex SoC and ASIC designs.
You will be responsible for planning, implementing, verifying, and optimizing DFT features to ensure high manufacturing test coverage, quality, and reliability of silicon products.
The role requires close collaboration with design, verification, physical design, and product engineering teams throughout the chip development lifecycle.
Candidates with experience in ATPG and MBIST methodologies will have an added advantage.
Key Responsibilities Define and implement DFT strategies for complex ASIC and SoC designs.
Develop and integrate scan architectures, including scan chain insertion, scan compression, and test point insertion.
Perform scan implementation and ensure proper integration within the design flow.
Collaborate with RTL, synthesis, and physical design teams to achieve DFT requirements while meeting timing and area constraints.
Validate DFT logic through simulation, verification, and debugging activities.
Generate and review DFT specifications, implementation plans, and test strategies.
Support silicon bring-up and debug activities related to test structures and manufacturing issues.
Analyze test coverage metrics and identify opportunities for optimization.
Work closely with ATPG teams to generate high-quality manufacturing test patterns.
Participate in design reviews and provide recommendations for testability improvements.
Ensure adherence to industry-standard DFT methodologies and best practices.
Develop scripts and automation solutions to improve DFT implementation efficiency.
Required SkillsMust-Have Skills Strong experience in DFT (Design for Testability) implementation and verification.
Hands-on expertise in Scan Implementation , including: Scan chain insertion Scan stitching Scan compression Scan architecture design Scan chain debugging and validation Good understanding of digital design fundamentals and semiconductor design flows.
Experience with RTL design, synthesis, and gate-level verification.
Knowledge of timing constraints and physical design considerations related to DFT.
Strong debugging and problem-solving skills.
Familiarity with scripting languages such as Tcl, Perl, Python, or Shell scripting.
Good-to-Have Skills Experience with ATPG (Automatic Test Pattern Generation) methodologies and tools.
Knowledge of MBIST (Memory Built-In Self-Test) architecture, integration, and verification.
Exposure to boundary scan, JTAG, and IEEE test standards.
Understanding of diagnosis, fault simulation, and yield improvement techniques.
Experience working on advanced technology nodes and large-scale SoC designs.
Qualifications Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, VLSI Design, Computer Engineering, or a related field.
3–10 years of industry experience in DFT engineering for ASIC or SoC development.
Proven experience delivering successful DFT implementations from design through silicon validation.
This job post has been translated by AI and may contain minor differences or errors.
