Job Details:Job Description: Candidate need to evaluate 3DIC technologies and propose areas of improvement , support internal customers by developing/proposing solutions and also interact with various EDA Vendors Synopsys, Cadence, Siemens, RedhawkSC and ungate the issues in convergence of 3D Stacked Dies. Candidate should generate test cases for validation of both Single and Multi Die configurations using TSV and Bumps collaterals and run through all flow DRCD/LVS/STA/EXTRACTION/RV/SI
Work also include Writing good document/report on PDK/ADF QA results and support DEV/PMs on aforementioned areas. Candidate should have good hands on exposure on automation TCL, Perl, Python and good understanding of 3DIC/low power/high speed ASIC PNR flows, Layout Verification and Timing Signoff methodologies. Candidate should be good communicator and self-driven individual. Candidate should have Willingness to adopt key changes as per specific customer needs and drive them to closure.
Qualifications:7+ Years of experience in PNR/APR domains with MTech/BTech degree
Candidate should have in-depth knowledge of the 3DIC Design requirements, ASIC technology files, ASIC RTL2GDSII flow development and QA. Candidate should have exposure to a breadth of EDA tools from different vendors.
Having experience in section/Full Chip STA will be added advantage
Candidate should have excellent interpersonal, analytical, written, and verbal communication skills; strong team player.Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
